publications

2026

1. 

   Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs

   Xiaoke Wang, Raveena Raikar, Markus Rein, and 3 more authors

   2026

   DOI
2. BenDan: Benchmarking DPU performance on FPGAs

   Han Bao, Xingyu Liu, Xiaoke Wang, and 6 more authors

   Integration, 2026

   Abs DOI Code

   The Deep Learning Processor Unit (DPU) has become a core component in general-purpose accelerators for efficiently deploying deep neural networks (DNNs) on Field-Programmable Gate Array (FPGA). To fully exploit DPU performance, guidelines are needed for DNN architecture design and model porting. Benchmarking is essential for understanding the DPU architecture and achieving its ultimate performance. However, existing DPU benchmarkings mainly focus on the network-level, lacking a fine-grained analysis that helps fully reveal the performance of the DPU. To this end, we propose BenDan, an operator-level benchmarking framework for DPU. BenDan can identify characteristics in key DNN operators such as fully connected layers and 2D convolution layers. It bridges the gap between theoretical specifications and actual performance through fine-grained, operator-level benchmarks on DPU. By collecting critical metrics, BenDan reveals inefficiencies caused by misalignment with the DPU’s pixel, input channel, and output channel parallelism. Moreover, we evaluate the DPU’s compatibility with cutting-edge neural network models to expose limitations in operator support and inform deployment strategies. The following key findings are observed: (1) Some specific operators may cause the performance loss of the DPU; (2) Among various factors, DPU architecture configuration has the most significant impact on performance, outweighing channel and pixel parallelism settings. (3) Cutting-edge NN layers are partially offloaded to the CPU. BenDan provides a practical tool for DPU-aware optimization and model refinement. BenDan can be easily generalized to all DPU releases, and the DPUCZDX8G is used as an example in this paper. The benchmarking framework is available on GitHub∗.

2025

1. 

   Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs

   Xiaoke Wang, and Dirk Stroobandt

   In Proceedings of the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2025), 2025

   DOI

2. 

   Adaptive Elite Learning Particle Swarm Optimization Algorithm with Complementary Sub-Strategies for Multimodal Problems

   Qianbo Lu, Jiaxin Sun, Zhenshan Wang, and 9 more authors

   SCIENCE CHINA Information Sciences, 2025

   Available online: Jul 3, 2025

   DOI

3. 

   Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy

   Xiaoke Wang, and Dirk Stroobandt

   In 2025 International Conference on Field Programmable Technology (ICFPT), 2025

   DOI
4. Interconnection-Aware Resynthesis for Improving FPGA Physical Design

   Xiaoke Wang, and Dirk Stroobandt

   In 2025 35th International Conference on Field-Programmable Logic and Applications (FPL), 2025

   DOI

2024

1. 

   A Novel Connection-Based Multicasting Router for Programmable Photonic Circuits

   Xiaoke Wang, Ferre Vanden Kerchove, Raveena Raikar, and 3 more authors

   Journal of Lightwave Technology, 2024

   Abs DOI

   In the rapidly evolving domain of Photonic Integrated Circuits, reconfigurability is making strides through tunable waveguide elements, facilitating ‘general-purpose’ programmable waveguide grids. Routing in modern programmable photonic networks is challenging due to the numerous possibilities that exist for assigning photonic circuits in the grid. Especially the necessary scaling to devices with many more photonic elements calls for more advanced routing heuristics. We can leverage on the existing routers for electronic reconfigurable systems (FPGAs), such as the PathFinder. However, it is crucial to connect network elements while adhering to optical signals’ physical restrictions. This complexity requires careful planning for smooth, error-free connections in the network infrastructure. This paper proposes a novel algorithm addressing routing challenges in programmable photonic circuits, specifically multicasting (single-source-multiple-sink) scenarios. Efficiently conserving the overall utilized routing resources stands as a crucial objective in programmable photonics routing. Our algorithm adeptly tackles multicasting routing problems with a particular focus on shortest pathlength multicasting routing. In contrast to the PathFinder, our algorithm demonstrates notable performance in optimization speed and the utilization of routing resources.

2. 

   The Influence of Interconnection Complexity on the FPGA CAD Flow

   Xiaoke Wang, and Dirk Stroobandt

   In Proceedings of the 2024 ACM International Workshop on System-Level Interconnect Pathfinding (SLIP ’24), Newark, NJ, USA, 2024

   Abs Code

   Moore’s Law has been guiding the development of the VLSI industry for the past half-century. This law underscores fabrication technology’s crucial role in enhancing chip performance. However, with technology nearing physical limitations, we envisage that there is still significant potential for optimizing interconnection complexity in VLSI design.Interconnection complexity is characterized by Rent’s Rule and the Rent exponent. We propose a new recursive normalized approach that can measure the Rent exponent accurately by eliminating the imbalance between blocks of different sizes. Then we demonstrate that optimizing the Rent exponent of the FPGA netlist can yield substantial benefits throughout the CAD flow process, particularly in physical design. By employing the GNL synthetic netlist generator to control interconnection complexity, we observe that a lower Rent exponent results in reduced running time, total wirelength and area usage. We also include real-world circuits from the Koios 2.0 benchmark suite in our analysis. The run-time of packing, placement and routing are ranging from exponential to double-exponential with respect to the Rent exponent. Our study highlights the significant impact of interconnection complexity on the EDA physical design flow. The results suggest that optimizing the netlist’s interconnection structure during logic synthesis or packing to reduce complexity could enhance the efficiency and performance of the EDA flow.