I am a third year Ph.D. researcher at Ghent University, and a member of the UGent Hardware Embedded System (HES) team at the CSL lab, where I have been advised by Prof. Dirk Stroobandt since Oct. 2023. I received my MSc in Electrical Engineering from Ghent University in 2023.
My current work studies how netlist interconnect structure affects FPGA packing, placement, and routing, with an emphasis on reducing physical-design bottlenecks in multi-die FPGA systems. I am open to research collaboration in related areas. You can find more details in my publications.