publications

2025

1. 

   Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs

   Xiaoke Wang, and Dirk Stroobandt

   2025

   DOI

2024

1. 

   A Novel Connection-Based Multicasting Router for Programmable Photonic Circuits

   Xiaoke Wang, Ferre Vanden Kerchove, Raveena Raikar, and 3 more authors

   Journal of Lightwave Technology, 2024

   DOI

2. 

   The Influence of Interconnection Complexity on the FPGA CAD Flow

   Xiaoke Wang, and Dirk Stroobandt

   In Proceedings of the 2024 ACM International Workshop on System-Level Interconnect Pathfinding, Newark, NJ, USA, 2024

   Abs DOI

   Moore’s Law has been guiding the development of the VLSI industry for the past half-century. This law underscores fabrication technology’s crucial role in enhancing chip performance. However, with technology nearing physical limitations, we envisage that there is still significant potential for optimizing interconnection complexity in VLSI design.Interconnection complexity is characterized by Rent’s Rule and the Rent exponent. We propose a new recursive normalized approach that can measure the Rent exponent accurately by eliminating the imbalance between blocks of different sizes. Then we demonstrate that optimizing the Rent exponent of the FPGA netlist can yield substantial benefits throughout the CAD flow process, particularly in physical design. By employing the GNL synthetic netlist generator to control interconnection complexity, we observe that a lower Rent exponent results in reduced running time, total wirelength and area usage. We also include real-world circuits from the Koios 2.0 benchmark suite in our analysis. The run-time of packing, placement and routing are ranging from exponential to double-exponential with respect to the Rent exponent. Our study highlights the significant impact of interconnection complexity on the EDA physical design flow. The results suggest that optimizing the netlist’s interconnection structure during logic synthesis or packing to reduce complexity could enhance the efficiency and performance of the EDA flow.